HV-CMOS Multi-chip and Serial Powering Prototyping

by Fuat Ustuner (University of Edinburgh)

Wednesday 17 Dec 2025, 09:00 → 10:00 Europe/Berlin

CP-03-123 (TU Dortmund)

High-voltage CMOS (HV-CMOS) technology is one of the latest technologies used for tracking detectors. They provide cost-effective high radiation tolerance, fast charge collection and low power consumption. HV-CMOS is a full commercial process that is suitable for large-area applications. The integrated sensor and readout design also allow for much easier detector assembly, compared to the hybrid pixel detector technology. These advantages make them one of the promising solutions for particle tracking detector development in high-energy physics experiments.

ATLASPix3.1 chip is the first full reticle size monolithic HV-CMOS sensor including two shunt low-dropout (LDO) regulators. It comprises 132x372 pixels with a pitch of 50μm x 150μm, fabricated using TSI 180nm HV-CMOS technology. The shunt-LDO regulators enable chip operation via serial powering. Serial powering involves using a single constant-current source to operate multiple chips in a chain. This approach is aimed at minimising the current consumption, and therefore the overall power consumption, with a focus on efficiency and
sustainability in electrical distribution materials.

The multi-chip quad module system, comprising four ATLASPix3.1 chips within a 4x4 cm2 area, facilitates shared powering and data transmission. Due to the multi-chip quad module structure, its integration of the serial powering schema, and the array of benefits it offers, these modules prove highly advantageous for large-scale applications.

This presentation will provide an overview of the characterisation results obtained with the single ATLASPix3.1 chip within the serial-powering framework and summarise the developments and design improvements introduced in the quad-module architecture. In addition, detailed performance results of the shunt-LDO regulators in the quad-module configuration and the corresponding readout behaviour of the system when operated in serially powered mode will be presented. Finally, the ongoing prototyping activities for multi-quad-module structures will be outlined, and the overall powering stability and readout performance demonstrated with the complete multi-chip quad-module system will be discussed.

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